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MIPI-Alliance released I3C-SenseWire specification for Sensor based application

Dear Friendsssss ,

Wafer Space is Hiring for Verification Engineers.

Check the below requirements:

SoC + UVM Experience

Must Have:
2 to 15+ years of prior work hands-on work experience
SoC Experience
Languages: System Verilog
Methodology: UVM

Must Have at least one of the below protocols:
USB2.0/USB3.0/ DDR2/DDR3/DDR4, Ethernet/ PCIe/ Video standards

Networking Verification.

Ethernet/OTN/MAC/WLAN/DDR/PHY/PCI/VERA/PCI/PCIE Verification/LIN/PON/10G/40G/100G/OVM/VM/UVM Verification (3 -15+ yrs)
Out of this any Protocols is fine with us.

Specman Verification Engineer.

4+ years relevant work experience (DDR/FLASH/PCIe/High Speed Interface Verification)
Develop test plans & test benches at the block/chip level using Specman e with eRM/UVM
Develop sequences & tests according to the verification test plans to verify these designs.
Able to develop functional coverage model & assertions
Strong analytical & debug skills.

DDR Verification Engineer.

• Expertise in industry standard methodologies like OVM/UVM/VMM.
• Expertise in writing the Verification plan, test plan and the functional coverage bins and executing them.
• Excellent Verilog and logic design concepts.
• Knowledge of memory controllers such as DDR2/DDR3/DDR4, LPDDR3/4, QDR, RLDRAM and buses like AXI/AHB.
• Strong working knowledge of UNIX environment and scripting languages such as Perl.
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi and ModelSim.

SOC Verification Engineers.

1) Soc verification Profile with extensive hands-on experience on Multimedia SoC
2) Must have experience with AXI,OCP,AHB,APB protocols
3) Processor driven Verification experience for at least 2+years
4) SV,Specman,SVA language expertize added bonus
5) Must have experience with trace and debug components like ATB,AMBA,ETF, Trace arbiter logic
6)Must be aware of ARM trust zone mechanism and its verification
7)Multimedia experiences - H.264,Encoder,Decoder,Display Verification in Subsystem or SOC level
8)Should have verified atleast one Multi-media block/system level verification
9) Scripting skills like Perl,Python,TCL is mandatory
10) Graphics processor verification or GPU integration verification in past is added bonus
Exp: 3-8 +yrs.

Networking Verification.

• Should have worked on developing/implementing test plans at the chip-level for a multi-million gate complex ASICs.
• Fluent in System Verilog, Verilog, Object oriented programming including C++ and scripting languages (Perl and Tcl/Tk).
• Must have intimate knowledge of UVM, OVM, or VMM simulation methodologies.
• Experience with code coverage and functional coverage; familiarity with evolving verification methodologies.
• Lab bring-up experience is desired.
• Good understanding of networking protocols/standards such as Ethernet or OTN.
• Very good communication skills and ability and desire to work in a geographically diverse team environment

Desired Skills
SV/UVM, Good Verification experience at SoC level/OTN, 10G/100G domain experience
Experience-5+yrs Onwards.

Recommend/Spread a word/Refer it to your Friends/Colleagues.

About Company:

Wafer Space was founded with the ideals of providing true value in Product and Design Services to all clients. Our world class engineering team with its intensive knowledge in Chip Design, Embedded Software and Hardware combined with ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates us. Wafer Space have achieved this by building a team of top talent and by having a strong focus on R&D. Have developed own flows & processes and focused on working in areas of high complexity in Chip Design & Embedded Systems.

Thanks & Regards,
S Jaya Shankar
Staffing-Lead

Wafer Space
N0.3/E, 5th Floor, Monarch Ramani,3rd Cross,7 th C Main Rd, Koramangala ,3rd Block,Bangalore -560034, India
Tel: +91 80 46720024| Mob: +91 8105211441 | Email: jayashankar@waferspace.com
Landmark: Near Toshiba & Flipkart

Wafer Space - New Office Link



















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SystemVerilog tutorial....

Provides easily understandable example codes and links to examples on edaplaygrond.

You can execute the example codes on the fly, on your web browser...

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Driving strength in decreasing order.
If you see "X" on the bus then there may be possibility of multiple driver.
if so, then both driver will be driving opposite value with equal strength.

for example:
                 one driver is driving "1" with "strong1" strength and
                 other driver is driving "0" with "strong0" strength.
Photo

Free EDA tools to generate SystemVerilog Interface and a complete testbench, UVM environment and more at www.VerifWorks.com 
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