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After repeated requests from EDA vendors to discuss how we at Cavium have successfully used and deployed UVM, I decided to write this book. Cavium’s small team has produced over a dozen very large and complex SoCs: Octeons®, Thunders®, Neurons®, and Nitroxes®. Cavium’s verification engineers write their own environments with minimal usage of Verification IP.
We have succeeded with thorough guidelines and advanced strategies that maximize re-use and optimize simulation speed to achieve first-pass silicon.

Advanced UVM will take you and your organization to  the next level of your verification education.

Free EDA tools to generate SystemVerilog Interface and a complete testbench, UVM environment and more at 

Hi Cool people,

Hope you all are having good weekend.

_Yash Shah
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