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TUTORIAL 7 – VERY POPULAR
Mixed-signal DFT and BIST: Trends, Principles, and Solutions
Presenters S. Sunter
Description: We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing, such as reducing costs that are increasingly dominated by MS functions. Next, we discuss trends in standardized DFT, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with a review of DFT/BIST techniques, including fault simulation. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and briefly RF. Next seven essential principles of practical analog BIST are presented in detail. Lastly, we discuss the most-practical DFT and BIST techniques, ranging from the classic analog bus, to mostly-digital oversampling and undersampling methods that greatly improve range, resolution, and reusability. Examples and case studies are included. Attendees will gain a clear picture of where they are keeping up with industry, the roadblocks to analog BIST adoption, and how to make parametric DFT/BIST, diagnosis, and testing more systematic. http://ow.ly/e6vGG
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Visit Evaluation Engineering on the exhibits floor at ITC. See http://bit.ly/na5GBA to find out who else is exhibiting. #itctestweek
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ITC Proceedings Boxed Sets For Sale at ITC2012
The International Test Conference is proud to offer box sets of conference proceedings from the past 5 years, 2007 – 2011 inclusive. Each box set includes 5 CDs.

The price for each box set is $100, quantities are limited and are available exclusively at ITC2012 conference. Starting this year, this material will only be available online, so don’t miss the opportunity to catch up on any years you might have missed.

Purchase of ITC box sets is managed on the registration area of the website. Box sets can be ordered online through the ITC Registration Page. These must be picked up at ITC2012 registration desk. Quantities are very limited, so order now.
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We are working on a Call for Posters announcement to put on our website and send out as an email blast. If you have any ideas for this event, please get ready to submit your proposal. Deadline will be Friday, July 6
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Have them in circles
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Arun Balachandar's profile photo
 
ITC registration opens in 30 minutes. Today's registration hours are 7:30 am to 5:00 pm.
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VERY POPULAR TUTORIAL at ITC on Monday Nov 5 - Don't miss it, registration discount available through Friday, October 5
Delay Test: Concepts, Theory and Recent Trends
Presenters S. Natarajan , A. Sinha
Description: This is an advanced tutorial covering fundamental concepts, research ideas and industry practices on validating and testing integrated circuits for speed failures. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test.
The tutorial starts with a discussion of defects and design marginalities that induce a circuit to fail at its rated speed while passing at a lower speed. This is followed by fault models and fault sensitization conditions, covering classical models such as transition faults and path delay faults, and models that capture crosstalk, voltage droop, multiple-input switching and charge-sharing. It then discusses test generation, fault simulation and diagnosis algorithms. design-for-test techniques that facilitate application of delay tests, metrics to measure test quality, and techniques to improve test quality and reduce yield loss are then discussed. Finally, applications in post-silicon validation, speed binning and in-field reliability are discussed using industry case studies.
http://ow.ly/eaYFm
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ITC Proceedings Boxed Sets For Sale at ITC2012
The International Test Conference is proud to offer box sets of conference proceedings from the past 5 years, 2007 – 2011 inclusive. Each box set includes 5 CDs.

The price for each box set is $100, quantities are limited and are available exclusively at ITC2012 conference. Starting this year, this material will only be available online, so don’t miss the opportunity to catch up on any years you might have missed.

Purchase of ITC box sets is managed on the registration area of the website. Box sets can be ordered online through the ITC Registration Page. These must be picked up at ITC2012 registration desk. Quantities are very limited, so order now.
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ITC tutorials continue to provide outstanding value for all who attend. Discount rates are only $395 for IEEE members, $495 for non-members through October 5. After October 5, non-discount rates apply.
 
This years tutorial offering are:

Sunday, November 4
#1: Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability.
#2: Practices in Analog, Mixed Signal and RF Testing
#3: Demystifying Board-Level Test and Diagnosis
#4: Power-aware Testing and Test Strategies for Low-Power Devices
#5: Testing Memories in the Nano-Era: Fault Models, Test Algorithms, Industrial Results, BIST and BISR
#6: The Economics of Test and Test and Testability

Monday, November 5
#7: Mixed-signal DFT and BIST
#8: Delay Test: Concepts, Theory and Recent Trends
#9: Statistical Adaptive Test Methods Targeting “Zero Defect” IC Quality and Reliability
#10: Bridge to Moore – IEEE Standards Provide Access to Debug, Validation and Test of Evermore Complex ICs; on ATE, on Board and in System
# 11: Testing TSV-based 2.5-D and 3-D Stacked ICs
#12: Best Methods and Techniques for Understanding and Optimizing Wafer Sort
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A Call for Posters was issued today. Go to the link for more information,and even better submit a proposal for a poster. ITC  will be held Nov 4 - 9 at the Disneyland Hotel in Anaheim California.
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Story
Tagline
Premier conference for Test Engineering professionals from Industry and Academia.
Introduction
WELCOME TO ITC's BRAND PAGE

International Test Conference is the world's premier venue dedicated to the electronic test of devices, boards and systems. ITC covers the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, failure analysis and back to process and design improvement. At ITC, design, test, and yield professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

ITC, the cornerstone of the Test Week™ event, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, a lecture series, commercial exhibits and presentations, and a host of ancillary professional meetings.

Please join us in November when we return to the Disneyland Hotel in Anaheim California.