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Hesham Almatary
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A talk about my #GSoC project with #lowRISC - #ORCONF Conference 2015
It was great to give a talk about my Google Summer of Code project with lowRISC at the fourth instance of ORCONF conference held this year in CERN, Geneva, Switzerland. ORCONF is concerned with open-source digital design hardware and embedded systems, motiv...
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New sel4test and sel4bench releases supporting SiFive's Unleashed Platform
In Brief: New features: A new option to run seL4 in machine mode. Ported seL4 to QEMU's SiFiveU and virt platforms. DTB parsing in seL4 to read and use UARTs when available. Ported seL4 to run on VC707 FPGA Freedom Unleashed platform. Initial Benchmarking s...
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IPC Perfoamnce of seL4 microkernel on RISC-V Cores
I managed to get Freedom Unleashed U500 and Boom synthesized on VC707 FPGA Board. This motivated me to port seL4 to run there and do some microbenchmarking using sel4bench project. Note that the seL4/RISC-V port is still a prototype, yet it can compete with...
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RISC-V RTEMS port is Upstream
Introduction Having the RISC-V 's GCC and Binutils upstream, as well as the increasing popularity and support RISC-V is getting pushed us to upstream RTEMS /RISC-V port, and it is gonna be part of the upcoming major RTEMS release. RTEMS (The Real-Time Execu...
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[Update] seL4/RISC-V SMP support | seL4 Tutorials release to RISC-V
Updates (since 03062017)   A new unofficial 24062017 release of seL4, libraries and seL4 Tutorials. SMP support, tested on Spike with 2 - 9 cores: seL4 is using a big kernel lock . Only reschedule IPI (set affinity) is provided. Relying on SBI to do other r...
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sel4test/RISC-V unofficial release - priv-1.10 - spec-2.3
Major updates since 2015 - It's now based on seL4's master (rather than experimental) branch, which means it makes use of architecture-independent verified code. - Instead of earlier 32-bit support, it's now based on 64-bit RISC-V. - Compatible with latest ...
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RTEMS port for RISC-V, with/without seL4 support
This is a brief update about RTEMS port progress to RISC-V. RTEMS port for RISC-V architecture (currently riscv32) runs Hello World and Ticker (with sim timer), on both Spike simulator and seL4 microkernel (two cores). The github repo of the port is here [1...
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[HOWTO] Build and run seL4 on RISC-V targets
This post gives instructions how to build seL4 to run on RISC-V targets (currently Spike simulator and Rocket Chip/FPGA). The default, and currently only, application is SOS [1] which is a simple operating system running on top of seL4. This means other sim...
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