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MEKALA RAMARAO
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DO UR BEST INSPIRE THE REST
DO UR BEST INSPIRE THE REST

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Verilog Behavioral Program for Counters
UP COUNTER (4 BIT) : module
upcount(clk,clr,q); input
clk,clr; output
[3:0]q; reg
[3:0]tmp; always@(posedge
clk or posedge clr) begin if(clr) tmp<=4'b0000; else tmp<=tmp+1'b1; end assign
q=tmp; endmodule DOWN COUNTER (4 BIT) : module
downcount(clk,clr,q); i...
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Verilog Behavioral Program for Flip Flops
SR FLIP FLOP : module
srflipflop(clk,S,R,Qnew,Qprev); input
clk,S,R; output
reg Qnew,Qprev=0; always@(posedge
clk) begin if(~S&~R) Qnew<=Qprev; else
if(S&~R) Qnew<=1; else
if(~S&R) Qnew<=0; end endmodule D FLIP FLOP : module
dflipflop(D,clk,clr,Q); input
D,...
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