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Microelectronics Research Group, Bristol
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Leading innovative research into Energy Aware COmputing (EACO)
Leading innovative research into Energy Aware COmputing (EACO)

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Microelectronics Research Group, Bristol's posts

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The hacking continues. Here's one of our 16-core boards and a peripheral board with some RAM on it (there's a version with an Ethernet adapter slapped onto it too - with a proper version of that on the way as well).

The peripheral board is connected (via a hacked cable for pin compatibility) to the bottom-right corner of the 16-core "Swallow" board. From there it can initialise all the cores in the grid and setup the routing tables. The cores are now sitting waiting to be sent programs via X-Link - no more programming over super-slow JTAG.

The JTAG plugged into the Swallow board is just to monitor stuff for debugging. The green wire is just adding a pull-up and the yellow is to allow the peripheral board to issue a reset to the Swallow grid.

The code, which still needs a fair bit of work to be usable, is on Github - https://github.com/stevekerrison/sw_swallow_xlinkboot - and was built in such a way that means parts of it will be useful for booting other large arrays of XMOS chips in this way (those parts will probably get forked into their own project once the API is stable enough).
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More manycore activity...
Here's a delightfully low quality photo, but trust me when I say that it shows an arrangement of 2x3x16 core boards, plus a board with a single core, flash and RAM on it. That's 97 cores in total. Hopefully it'll be ready to run something useful in a few days!
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112 +XMOS XS1 cores running in a 7-high stack of our many-core research boards. More info and pictures: http://www.cs.bris.ac.uk/Research/Micro/news.jsp#news_1342396800000

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It's exciting for us to be involved in this huge GPU supercomputing project... and now it's in service!

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AMD's Fusion APUs, with a GPU and x86 CPU, will also be getting an ARM Cortex A5!

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Real-time supercomputing?
I've run out of desk and cables, but not before booting 80 XMOS cores in a single system on a mesh network. This is, as far as I am aware, the largest number of XS1 processors ever assembled into a system; larger than the 64-core G-series based XMP-64 which assembles its quad core chips into a hypercube. These boards have eight dual-core L-series chips and form quite an interesting mesh topology by virtue of their on-chip connectivity and the links that are exposed on the package. I could build more boards out horizontally, but I need more cables... and a better way of powering them ;)
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