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mark gross
Works at intel
Attended university of northern iowa
Lives in pdx
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mark gross

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Timothy Chen's profile photo
 
Nice photos.  My old high school was within walking distance of the Sands hotel.  Singapore has really changed.
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mark gross

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Walking back from dinner on my first night in munich I stopped at a "quickshop" like place just to look around and saw this can and had to buy one.

Tastes a bit like hamms but more bitter.

mmm good.
8
1
Sriram Ramkrishna (sri)'s profile photovιcтor panтoja's profile photo
 
got youself a can of 'hell yeah!' :)  I need a couple of those!
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perfect morning!
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Chandrasekaran Swaminathan's profile photo
 
Nice snap
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recovered my c710 using a dediprog borrowed from work, and spent lastnight and today hacking on the thing trying multiple coreboot config combonations before I got the bright idea to check if I should update the FW on my 5 year old SSD....  yup.  that made a big difference in the probing success in the boot sequence.

I blogged some of the details.  (if you ever need to jumper wire between the SPI-NOR on a C710 and a clip on by hand I have the pin outs documented for you.)  http://thegnar.org/sync/?p=356
3 weeks ago I buggered up my C710 after trying to get coreboot with a grub2 payload to boot on my laptop with an older Intel SSD. I've been having issues with the SSD not getting seen by the coreboot payloads without some funny busyness (more on this issue later.) Anyway after bricking it I put ...
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mark gross's profile photoMaksim Lin's profile photo
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Thanks +mark gross according to that it in theory should work with latest version of flashrom, I guess I'll punt and just get the v3 for now as and get the v4 if I ever I need the extra features.
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Having a great nerd weekend!  yesterday I built gnuradio and grqx and got basic use of the DVB dongle as SDR wiggling.  This morning I took to building and flashing coreboot on my C710.  It was going so well...

until I tried the grub2 payload and now I see the thing startup but looks to hang without display after jumping to the payload.

Now I need to crack the thing open and try to re-flash spi chip with  the last known working payload.  (see ehci debug trace below)

I'll come back to this next weekend.  I have some quilt tree to refresh.



COREBOOT   acfed400CBFS: located payload @ fff328f8, 273770 bytes.Loading segment from rom address 0xfff328f8
  code (compression=1)
  New segment dstaddr 0x8200 memsize 0x1aba4 srcaddr 0xfff3294c filesize 0x93e8
  (cleaned up) New segment addr 0x8200 size 0x1aba4 offset 0xfff3294c filesize 0x93e8
Loading segment from rom address 0xfff32914
  code (compresstaddr 0xed up) New segment addr 0x100000 size 0xb95d4 offset 0xfff3bd34 filesize 0x3992e
Loading segment from rom address 0xfff32930
  Entry Point 0x00008200
Bounce Buffer at acdae000, 1185292 bytes
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001aba4 filesz: 0x00000000000093e8
lb: [0x0000000000100000, 0x0000000000168038)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001aba4 filesz: 0x00000000000093e8
using LZMA
Clearing0x00000075 memsz000000007a2f
dest 00008200, end 00022da4, bouncebuffer acdae000
Loading Segment: addr: 0x00000005d4 filesz: 0x0000000000lb: [0x0000000000100000, 0x0000000000168038)
segment: [0x0000000000100000, 0x000000000013992e, 0x00000000001b95d4)
 bounce: [0x00000000acdae000, 0x00000000acde792e, 0x00000000ace675d4)
Post relocation: addr: 0x00000000acdae000 memsz:000000b95d4 filesz: 0x00using LZMA
[ 0xacdae000, ac0xace675d4) <- fff3bd34dest acd5d4, bouncebuffer acdae000
move suffix around: from ace16038, to 168038, amount: 5159c
Loaded segments
PCH watchdog disabled
code at 00008200
CPU0: stack: 00163000 - 00164000, lowest used address 00163a80, stack used: 1408 bytes
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x000buffer   = 0xacd
2
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Have him in circles
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mark gross

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Went on a hike in Singapore this afternoon.  http://www.wildsingapore.com/places/ttw.htm my feet hurt but it was worth it.  In the end I think I walked about 8Km but it felt like 10 miles.  I was drenched.  its very hot and humid here.

I saw a monkey scratching his balls,  I just missed the shot by 2 seconds.
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Sriram Ramkrishna (sri)'s profile photo
 
Just think what kind of memes we could make with that :)
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motly fool has just waisted 1hr of my time with a never fucking ending teaser message that rambles on an on and on over some company they refuse to identify that may grow 2000% by 2020 that will be a player as a backbone of the "internet of things" that is taking shape and I want my fucking 1hr back.  

I made it to the point where they started playing some clip of a husband/wife couple investors blowing about how good MF has been for them. (again without identifying the special company)

Its worse than sitting though a hard sell for a fucking time share.  I want hr back! FU MF for waisting my time.

I wonder if its all a marketing experiment to see how much abuse a possible customer can handle before saying enough!

if someone makes it to the end of this fucking never ending story without shooting themselves can you share what this magic stock pick is?
http://www.fool.com/video-alert/stock-advisor/sa-internetofthings-ext/?source=isasiteml0910232&u=1949558382

All I got to say is die you bastards for wasting my time.
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Robert Ranslam's profile photoJim Larson's profile photomark gross's profile photo
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I agree.
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mark gross

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I bet it seemed like a good idea to him when she asked if she could try face painting on him.

Fun at the cedar mill farmers market.
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Alan Olsen's profile photo
 
Just don't get face painting done at Home Depot. They use a roller.
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mark gross

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Well, I've gone and done it now.

I was trying to follow different instructions on building the coreboot (seabios payload) for a C710 2833 that has 8GB ram and an intel 160GB SSD (yeah I know that is dumb but, I had it in a drawer so why not?)

anyway I was booting the http://johnlewis.ie/coreboot-parrot-grub2-suspend-27102013.rom image and bothered buy the following
1) I didn't compile it
2) it would "just work" from grub to locate the grub.cfg on the SSD without first failing and then failing over to the sea bios which did work (but only if grub tries and fails very odd.)

So I followed both http://johnlewis.ie/compiling-your-own-coreboot-firmware-for-the-samsung-series-5-550-chromebook/ (but I deviated for building parrot) and https://docs.google.com/presentation/d/1eGPMu03vCxIO0a3oNX8Hmij_Qwwz6R6ViFC_1HlHOYQ/edit#slide=id.gf4036fef_079 

and with the seabios I got the same results  it (sort of) booted but could not access the SATA SSD to grub boot my native ubuntu 13.10 install installed on a legacy partition map.

I found I could boot the ubuntu installer USB key mount and and then chroot to the SSD file system and do some tweaking and recompiling.  so I did that.  

At some point I decided to try the grub2 payload.  Here I had a number of issues with getting the coreboot.rom to compile (sizes of payload I think) and finally got a build to go through.

I flashed the grub2 payload and found that I've hosed it.  

Is there any special things to be aware of when building with a grub2 payload I overlooked?

Next weekend I'll take a dediprog home for the weekend and re-flash the spi.  But, before I do that I would like to know if anyone has seen any issues with a SSD not getting seen by seabios like above.

Also, I'd like to know the specific core boot FW git sha1 and config files used to build a working C710 coreboot from anyone else who has had any success.  If you are willing to share that would be very helpful ;)

FWIW the the EHCI debug output seems to work pretty well:

...

coreboot-4.0-5704-gfa02e16-mark97229 Sun Apr  6 12:22:48 PDT 2014 starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
Back from sandybridge_early_initialization()
SMBus controller enabled.
CPU id(206a7): Intel(R) Celeron(R) CPU 847 @ 1.10GHz
AES NOT supported, TXT NOT supported, VT supported
PCH type: NM70, device id: 1e5f, rev id 4
Intel ME early init
Intel ME firmware is ready
ME: Requested 16MB UMA
Starting UEFI PEI System Agent
Read scrambler seed    0x0000cde1 from CMOS 0x98
Read S3 scrambler seed 0x000073a3 from CMOS 0x9c
find_current_mrc_cache_local: picked entry 0 from cache block
prepare_mrc_cache: at fffd0010, size bb0 checksum e446
System Agent: Starting up...
System Agent: Initializing PCH
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USUSB
gent Version 1.2.2 Build Done with statuA base: 0x1ff0
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Host communication established
memcfg DDR3 clock 1333 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (006200   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 4096 MB width x8 dual rank, selected
   DIMMB 0 MB width x8 single rank
memcfg channel[1] config (00620010):
   ECC inactive
   enhanced inteve on
 4096 MBank, selnk
gion aceAdding CBMEM entry as no. 1
ry as no. 2
Adding CBMEM entry as no. 3
Adding CBMEM entry as no. 4
Relocate MRC DATA from ff7e3237 to acee0600 (2992 bytes)
Save scrambler seed    0x00007afe to CMOS 0x98
Save s3 scrambler seed 0x0000cde1 to CMOS 0x9c
Adding CBMEM entry as no. 5
Trying CBFS ramstage loader.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (426040 bytes), entry @ 0x100000
ug port  CBMEM.
coreboot-4.0-5707229 Sung...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: abled 1
PCI: 00:00.0: enabled 116.2: enabled 0abled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0

PCI: 00:abled 1
PCI: 00:abled 0
PCI: 00:1c.4: enabled 0
PCI: 00:abled 0abled 0
1d.0: enPCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 1
Compare with tree...
Root Devbled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
  APIC: acac: enabled 0
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:16.1: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:16.3: enabled 0
  PCI: 00:19.0: enabled 0
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 0
  PCI: 0enabled 1
  PCI: 00:1c.2: enabled 1
  PCI: 00:1c.3: enabled 0
  PCI: 00:1c.4: enabled   PCI: 00:1c.5: enabled 0
  PCI: 00:1c.6: enabled 0
  PCI: 00:1c.7: enabled 0
  PCI: 00:1d.0: enabled 1
  PCI: 00:1e.0: enabled 0
  PCI: 00:1f.0: enabled 1
   PNP: 00ff.1: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
  PCI: 00:1f.5: enabled 0
  PCI: 00:1f.6: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0104] ops
Normal boot.
PCI: 00:00.0 [8086/0104] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0106] enabled
PCI: 00:16.0 [8086/1e3a] bus ops
PCI: 00:16.0 [8086/1e3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1e3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:19.0: Disabling device
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1e2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1e20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0: Disabling device
PCI: 00:1c.0: check set enabled
PCH: Remap PCIe function 1 to 0
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/1e12] enabled
PCH: Remap PCIe function 2 to 0
PCI: 00:1c.2 [8086/0000] bus ops
PCI: 00:1c.2 [8086/1e14] enabled
PCI: 00:1c.3: Disabling device
PCI: 00:1c.4: Disabling device
PCI: 00:1c.4: check set enabled
PCI: 00:device
PCI: 00:1c.6: Didevice
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xfedcb10a
PCH: PCIe map 1c.0 -> 1c.2
PCH: PCIe map 1c.1 -> 1c.0
PCH: PCIe map 1c.2 -> 1c.1
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1e26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1e5f] enabledPCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/1e01] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1e22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.6 [8086/1e24]scan_static_bus for PCI: 00:16.0 done
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci
ing with 0x01 @ Capability: type 0x05 @ 0x50
 0x10 @  Common s and L1can_bridge returcan_bridc.1
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [14e4/16b5] enabled
PCI: 02:00.1 [14e4/16bc] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x48
Capability: type 0x05 @ 0x58
Capability: type 0x11 @ 0xa0
Capability: type 0x10 @ 0xac
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x01 @ 0x48
Capabili 0x05 @ 0x58
ty: type 0x10 @ 0xac
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
PNP: 00ff.0 enabled
tic_bus for PCI:tic_bus for PCI:tic_bus  00:1f.3_scan_bus return
scan_static_bus for Root Device done
done
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting GE_CTL_VGA for bridge Root Device
Allocating resou
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
More than one caller of pci_ehci_read_resources from PCI: 00:1a.0
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.1 read_resources bus 2 link: 0
PCI: 00:1c.1 read_resources bus 2 link: 0 done
PCI: 00:1d.0 EHCI BAR hook registered
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLU
USTER: 0n link 0
: 0000n link 0:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index 00:02.0
   PCI: resource000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
   PCI: 00:02.0 resource base 0 size 40 align 6 imit fff   PCI: 00:16.000:16.0 align 4 fffffffffffff flindex 1000:16.100:16.200:16.3
00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0  align 10 gran 10 limit ffffffff00 index 10
   PCI: 
   PCI: 00:1b.0  base 0 size 40014 gran 14 limitfffffffff flags x 10
   PCI: 00:1c.2
   PCI:  child on link 0:00.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI:e base 0 size 80000 aligit ffffffffffffffff flags 201 index 10
    PCI: 01:00.0e base 0 size 10n 16 gran 16 limit ffffffff flags 2200 i
00:1c.1n link 000:1c.1 size 0 agran 12 
00:1c.1 lign 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 10n 16 gran 16 limit ffffffffffffffff flags 1201 index 10
    PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 18
    PCI: 02:00.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 2200 index 30
    PCI: 02:00.1
    PCI: 02:00.1 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 10
   PCI: 00:1c.3
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 00ff.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base fd60 size 4 align 0 gran 0 limit 0 flags c0040100 index 10000200
    PNP: 00ff.1
    PNP: 00ff.0
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:02.0 20 *  [0x0 - 0x3f] io
PCI: 00:1f.2 20 *  [0x40 - 0x5f] io
PCI: 00:1f.2 10 *  [0x60 - 0x67] io
PCI: 00:1f.2 18 *  [0x68 - 0x6f] io
PCI: 00:1f.2 14 *  [0x70 - 0x73] io
PCI: 00:1f.2 1c *  [0x74 - 0x77] io
DOMAIN: 0000 compute_resources_io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0x7ffff] mem
PCI: 01:00.0 30 *  [0x80000 - 0x8ffff] mem
PCI: 00:1c.0 compute_resources_mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 10 *  [0x0 - 0xffff] prefmem
PCI: 02:00.0 18 *  [0x10000 - 0x1ffff] prefmem
PCI: 02:00.1 10 *  [0x20000 - 0x2ffff] prefmem
PCI: 00:1c.1 compute_resources_prefmem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 30 *  [0x0 - 0x7ff] mem
PCI: 00:1c.1 compute_resources_mem: base: 800 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:*  [0x0 - 0xfffffff] prefmem
PCI: 00:02.0 10 *  [0x10000000 - 0x103fffff] mem
PCI: 00:1c.0 20 *  [0x10400000 - 0x104fffff] mem
PCI: 00:1c.1 24 *  [0x10500000 - 0x105fffff] prefmem
PCI: 00:1c.1 20 *  [0x10600000 - 0x106fffff] mem
PCI: 00:1b.0 10 *  [0x10700000 - 0x10703fff] mem
PCI: 00:1f.6 10 *  [0x10704000 -fff] mem
PCI: 00:1f.2 24 *  [0x10705000 - 0x107057ff] mem
PCI: 00:1a.0 10 *  [0x10705800 - 0x10705bff] mem
PCI: 00:1d.0 10 *  [0x10705c00 - 0x10705fff] mem
PCI: 00:1f.3 10 *  [0x10706000 - 0x107060ff] mem
PCI: 00:16.0 10 *  [0x10706100 - 0x1070610f] mem
DOMAIN: 0000 compute_resources_mem: base: 10706110 size: 10706110 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resourAIN: 0000
constrain_resour: 00:00.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:1a.0
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:1c.1
constraices: PCI: 02:00.constraices: PCI: 02:00.1
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 00ff.1
constrain_resources: PNP: 00ff.0
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
constrain_resources: PCI: 00:1f.6
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000fd5f
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
lim->base 00000000 lim->limit efffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:78 align:6 gran:0 limit:fd5f
Assigned: PCI: 00:02.0 20 *  [0x1000 - 0x103f] io
Assigned: PCI: 00:1f.2 20 *  [0x1040 - 0x105f] io
Assigned: PCI: 00:1f.2 10 *  [0x1060 - 0x1067] io
Assigned: PCI: 00:1f.2 18 *  [0x1068 - 0x106f] io
Assigned: PCI: 00:1f.2 14 *  [0x1070 - 0x1073] io
Assigned: PCI: 00:1f.2 1c *  [0x1074 - 0x1077] io
DOMAIN: 0000 allsources_078 sizegn: 6 grPCI: 00:1c.0 allocate_re:fd5f sign:12 grmit:fd5f
ocate_resources_io: next_base: fd5f size: 0 align: 12 grPCI: 00:1c.1 allocate_resources_io: base:fd5f size:0 alimit:fd5f
sources_io: nextn: 12 grone
DOMAIN: e:d0000000 size:10706110 align:28 gran:0 limit:efffffff
Assigned: PCI: 00:02.0 18 *  [0xd0000000 - 0xdfffffff] prefmem
Assigned: PCI: 00:02.0 10 *  [0xe0000000 - 0xe03fffff] mem
Assigned: PCI: 00:1c.0 20 *  [0xe0400000 - 0xe04fffff] mem
Assigned: PCI: 00:1c.1 24 *  [0xe0500000 - 0xe05fffff] prefmem
Assigned: PCI: 00:1c.1 20 *  [0xe0600000 - 0xe06fffff] mem
Assigned: PCI: 00:1b.0 10 *  [0xe0700000 - 0xe0703fff] mem
Assigned: PCI: 00:1f.6 10 *  [0xe0704000 - 0xe0704fff] mem
Assigned: PCI: 00:1f.2 24 *  [0xe0705000 - 0xe07057ff] mem
Assigned: PCI: 00:1a.0 10 *  [0xe0705800 - 0xe0705bff] mem
Assigned: PCI: 00:1d.0 10 *  [0xe0705c00 - 0xe0705fff] mem
Assigned: PCI: 00:1f.3 10 *  [0xe0706000 - 0xe07060ff] mem
Assigned: PCI: 00:16.0 10 *  [0xe0706100 - 0xe070610f] mem
DOMAIN: 0000 allocate_resources_e0706110 size: 10706110 align: 28 gran: 0 done
PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: bas00 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 01:00.0 10 *  [0xe0400000 - 0xe047ffff] mem
Assigned: PCI: 01:00.0 30 *  [0xe0480000 - 0xe048ffff] mem
PCI: 00:1c.0 allocate_resources_mem: next_base: e0490000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_prefmem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 02:00.0 10 *  [0xe0500000 - 0xe050ffff] prefmem
Assigned: PCI: 02:00.0 18 *  [0xe05100001ffff] prefmem
Assigned: PCI: 02:00.1 10 *  [0xe0520000 - 0xe052ffff] prefmem
PCI: 00:1c.1 allocate_resources_prefmem: next_base: e0530000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_mem: base:e0600000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 02:00.0 30 *  [0xe0600000 - 0xe06007ff] mem
PCI: 00:1c.1 allocate_resources_mem: next_base: e0600800 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x24f600000 TOLUD 0xafa00000 TOM 0x200000000
MEBASE 0x1ff000000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0xad000000 size 8M
Available memory below 4GB: 2768M
Available memory above 4GB: 5366M
Adding PCIe config bar base=0xf0000000 size=0x4000000
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:16.0 10 <- [0x00e0706100 - 0x00e070610f] size 0x00000010 gran 0x04 mem64
PCI: 00:1a.0 10 e0705800 - 0x00e0705bff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00e0700000 - 0x00e0703fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000fd5f - 0x000000fd5e] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e047ffff] size 0x00080000 gran 0x13 mem64
PCI: 01:00.0 30 <- [0x00e0480000 - 0x00e048ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.1 1c <- [0x000000fd5f - 0x000000fd5e] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00e0500000 - 0x00e050ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 02:<- [0x00e0510000 - 0x00e051ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 02:00.0 30 <- [0x00e0600000 - 0x00e06007ff] size 0x00000800 gran 0x0b romem
PCI: 02:00.1 10 <- [0x00e0520000 - 0x00e052ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 00:1d.0 EHCI Debug Port hook triggered
PCI: 00:1d.0 10 <- [0x00e0705c00 - 0x00e0705fff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 EHCI Debug Port relocated
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x00000010600001067] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000001070 - 0x0000001073] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x00 - 0x000000106f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000001074 - 0x0000001077] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00e0705000 - 0x00e07057ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00e0706000 - 0x00e07060ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.6 10 <- [0x00e0704000 - 0x00e0704fff] size 0x00001000 gran 0x0c mem64DOMAIN: 0000 assign_resogion aceting resources.Show resources in subtree (Root Device)...After assignin.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAINesource base 1000 size 78 align 6 gran 0 limit fd5f flags 40040100 index 10000000
  DOMAIN: 0000 resource base d0000000 size 10706110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base 100000 size acf00000 align 0 gran 0 limit 0 flags e0004200 index 4
  DOMAIN: 0000 resource base 100000000 size 14f600000 align 0 gran 0 limit 0 flags e0004200 index 5
  DOMAIN: 0000 resource base ad000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
  DOMAIN: 0000 resource base f0000000 size 400000 flags f0000200 index 7
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
  DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
  DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit e000020   PCI: 00:02.0 resource base e01 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
   PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit fd5f flags 60000100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base e0706100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
   PCI: 00:16.1
   PCI: 
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base e0705800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base e0700000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
   PCI: 00:1c.2
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base fd5f size 0 align 12 gran 12 limit fd5f flags 60080102 index 1c
   PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base e0400000 size 80000 align 19 gran 19 limit efffffff flags 60000201 index 10
    PCI: 01:00.0 resource base e0480000 size 10000 align 16 gran 16 limit efffffff flags 60002200 index 30
   PCI: 00:1c.1 child on link 0 PCI: 02:00.0
   PCI: 00:1c.1 resource base fd5f size 0 align 12 gran 12 limit fd5f flags 60080102 index 1c
   PCI: resourcet efffffff flags 60081202 index 24
   PCI: 00:1c.1 resource base e0600000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base e0500000 size 10000 align 16 gran 16 limit efffffff flags 60001201 index 10
    PCI: 02:00.0 resource base e0510000 size 10000 align 16 gran 16 limit efffffff flags 60001201 index 18
    PCI: 02:00.0 resource base e0600000 size 800 align 11 gran 11 limit efffffff flags 60002200 index 30
    PCI: 02:00.1
    PCI: 02:00.1 resourc0520000 00 align 16 gran 16 limit efffffff flags 60001201 index 10
   PCI: 00:1c.3
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base e0705c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 00ff.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base fd60 size 4 align 0 gran 0 limit 0 flags c0040100 index 10000200
    PNP: 00ff.1
    PNP: 00ff.0
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 1060 size 8 align 3 gran 3 limit fd5f flags 60000100 index 10
   PCI: 00:1f.2 resource base 1070 size 4 align 2 gran 2 limit fd5f flags 60000100 index 14
   PCI: 00:1f.2 resource base 1068 size 8 align 3 gran 3 limit fd5f flags 60000100 index 18
   PCI: 00:1f.2 resource base 1074 size 4 align 2 gran 2 limit fd5f flags 60000100 index 1c
   PCI: 00:1f.2 resource20 alignfd5f fla100 inderesource705000 salign 110 align 0 gran 01f flags20
   PCI: 00:1f.3 resource base e0706000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base e0704000 size 1000 align 12 gran 12 limit efffffff flags 60000201 index 10
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 0000/0000
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:1a.0 subsystem <- 0000/0000
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 0000/0000
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 0000/0000
PCI: 00:1c.1 cmd <- 106
PCI: 00:1d.0 subsystem <- 0000/0000
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 0000/0000
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 103PCI: 00:system <- 0000/0000
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 02:00.1 cmd <- 06
done.
Initializing devices...
Root Device init
Parrot EC Init
  EC version 0.7  EC Project: KZV1V
  Parrot Revision de
CPU_CLUSTER: 0 istart_eip=0x00001000, co31
ng SMM handler t0000
eader to000
Initializing SMM handler ... pmbase = 0x0500

 PM1 PM1_STS: WAK PWRBTN 
GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI15 GPI14 GPI12 GPI11 GPI10 GPI9 GPI8 GPI6 GPI5 GPI4 GPI3 GPI0 
TCO_STS: 
  ... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
Enabling cache
microcode: sig=0x206a7 pf=0x10 revision=0x28
CPU: Intel(R) Celeron(R) CPU 847 @ 1.10GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad000000 size 0xacf40000 type 6
0x00000000ad000000 - 0x00000000d0000000 size 0x23000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000024f600000 size 0x14f600000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR xed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x060606060606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x06060606pe WB/UC MTRR counts: 6/11.
MTRR: WB selected as default type.
MTRR: 0 base 0x0d000000 mask 0x0000000fff000000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0
MTRR: 2 0000000b0000000 000000fftype 0
base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
MTRR: 4 0000000 mask 0x0000000ff0000000 MTRR: 5 0000000e0000000 mask 0x0000000fe0000000 
MTRR cRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
6ax: enemodel_x06ax: frequency set to 1100
Turbo is unavailable
CPU: 0 has 2 cores, 1 threads per core
CPU: 0 has core 2
CPU1: stack_base 00162000, stack_end 00162ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting  to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
zing CPU #1
Startup point 1.
 to finil device 206a7
Sending STARTUP #2 to 2.
After apic_write.
CPU: family 06, model 2a
Waiting Enabling cache
After Startup.
CPU #0 iWaiting for 1 CPUS to stop
microcode: sig=0x206a7 pf=0x10 revision=0x0
microcoded to revision 0=2012-040606060606060606

00000000MTRR: Fixed MSR 0x268 0x0606060606060606MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606MTRR: Fi0x26b 0x0606060606060606MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606xed MSR 0x26e 0x0606060606060606MTRR: Fi0x26f 0x0606060606060606
call enable_fixed_mtrr()
MTRR: 0 base 0x00000000ad000000 000000fff000000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0
MTRR: 2 base 0x00000000b0000000 mask 0x0000000ff0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 5 base 0x00000000e000000fe0000000 type 0
heck
Variable MTRRs: Enabled

up local apic... apic_id: 0x02 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 1100
CPU #1 initialized
All AP CPUs stopped (9027 loops)
CPU1: stack: 00162000 - 00163000, lowest used address 00162c34, stack used: 972 bytes
PCI: 00:00.0 init
Set BIOSPL
CPU TDP: 17 Watts
PCI: 00:02.0 init
GT Power Management Init
SNB GT1 Power Meter Weig ROM addPCI expansion ROture 0xaimage, vlass Code 030000, Code Type 00
Copying VGA ROM Image from fff00578 to 0xc0000, 0x10000 bytes
Real mode stub @00000600: 867 byCalling Option ROM...
ndler: I... Option ROM returned.
GT Power Managem (post V16.0 init
ME: FW Partition Table      : OK
ME: Briner Failure  : NO
ME: Firmware Init Complete  : YES
ME: Manufacturing Mode      : NO
ME: Boot Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Curration State : M0 with UMA
ME: Currde  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Host communication established
 path: Normal
ME: Extend SHA-256: ed931a410b99a2c8c57c310a9876d576bec64a7916a89221ae5c0d31
ME: MBP item header 00020103
ME: MBP item header 00050102
ME: MBP item header 00020501
ME: MBP item header 00020201
ME: MBP item header 02030101
ME: MBP item header 02060301
ME: MBP item header 02090401
ME: mbp read OK after 1 cycles
ME: found version 8.0.13.1502
ME Capability: Full Network manageability                : disabled
ME Capability: Regular Network manageability             : disabME Capability: Manageability                             : disabled
ME Capability: Small business technology                 : disabled
ME Capability: Level III manageability                   : disabled
ME Capability: IntelR Anti-Theft (AT)                    : disabled
ME Capability: IntelR Capability Licensing Service (CLS) :  enabled
ME Capability: IntelR Power Sharing Technology (MPC)     :  enabled
ME Capability: ICC Over Clocking                         :  enabled
ME Capability: Protected Audio Video Path (PAVP)         : disabled
ME Capability: IPV6                                      : disabled
ME Capability: KVM Remote Control (KVM)                  : disabled
ME Capability: Outbreak Containment Heuristic (OCH)      : disabled
ME Capability: Virtual LAN (VLAN)                        :  enabled
ME Capability: TLS                                       : disabled
ME Capability: Wireless LAN (WLAN)                       : disabled
PCI: 00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:1b.0 init
Azalia: base = e0700000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862806
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #0
Azalia: codec viddid: 10ec0269
Azalia: verb_size: 56
Azalia: PCI: 00:1c.0 init
 PCIe bridge.
PCI: 00:1c.1 init
Initializing PCH PCIe bridge.
PCI: 00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:1f.0 init
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
  reg 0x0000: 0x02000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
Set power off after power failure.
NMI sources disabled.
PantherPoint PM init
rtc_failed = 0x0
RTC Init
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x200
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
Locking SMM.
PCI: 00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: E0705000
PCI: 00:1f.3 iniPCI: 00:1f.6 init
PCI: 01:00.0 init
PCI: 02:00.0 init
PCI: 02:00.1 init
PNP: 00ff.0 init
Compal ENE932: Initializing keyboard.
Keyboard init...
Devices initialiShow all devs...Root Device: enaTER: 0: enabled : enableDOMAIN: 0000: enabled 1PCI: 00:00.0: en
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 116.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.2: enabled 0
PCI: 00:1c.1: en
PCI: 00:1c.3: en1c.4: en1c.5: en1c.6: en1c.7: enabled 0
PCI: 00:1d.0: enabled 11e.0: enabled 0
PCI: 00:1f.0: enf.1: ena1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 1
PCI: 01:00.0: enabled 1
PCI: 02:00.0: enabled 1
PCI: 02:
PNP: 00ff.0: enabled 1
APIC: 02: enabled 1
CBMEM region aced0000-acffffff (cbmem_check_toc)BMEM entry as noMoving Gee1400..ok
Finalize devices...
Devices finalized
Updating MRC cache data.
rent_mrcocal: picked entry 0 from cache block
 in flash is up  No update.
Adding CBMEM entry as noACPI: Writing ACs at acee1600.
ACPI:    * FACS
ACPI:   
ACPI:    * FADT
ACPI: ade 1/32, length nACPI:    * HPET
ACPI: added table 2/32, length now 44
ACPI:    * MADT
ACPI: added table 3/32, length now 48
ACPI:    * MCFG
ACPI: added table 4/32, length now 52
ACPI: Patching up global NVS in DSDT at offset 0x01ab -> 0xacee4e50
Adding CBMEM entry as no. 8
ACPI:     * DSDT @ acee1850 Length 341b
ACPI:     * SSDT
Found 1 CPU(s) with 2 core(s) each.
PSS: 1100MHz power 17000 control 0xb00 status 0xb00
PSS: 800MHz power 11938 control 0x800 status 0x800
PSS: 1100MHz power 17000 0xb00 scontrol ACPI: added table 5/32, length now 56
current = acee6670
ACPI: done.
ACPI tables: 20592 bytes.
Adding CBMEM entry as no. 9
smbios_write_tables: aceecc00
Root Device (Google Parrot)
CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
APIC: 00 (Socket CPU)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
PCI: 00:00.0 (Intel i7 (ridge) integrated NorthbSandyBridge/IvyBridge) integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (oint/Panther Point) Southbridge)PCI: 00:nt) Southbridge)
PCI: 00:16.2 (Intel Serither Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar P
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Serioint/Pannt) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Sout
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)f.1 (COMPAL ENE9PCI: 00:es 6/7 (1f.3 (Innt) Southbridge)
PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 01:00.0 (unknown)
PCI: 02:00.0 (unknown)
PCI: 02:00.1 (unknown)
PNP: 00ff.0 (unknown)
APIC: 02 (unknown)
SMBIOS tables: 353 bytes.
Adding CBMEM entry as no. 10
Adding CBMEM entry as no. 11
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 7edf
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xacfed400
rom_table_end = 0xacfed400
... aligned to 0xacff0000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-00000000000AM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000001fffffff: RAM
 4. 0000000020000000-00000000201fffff: RESERVED
 5. 0000000020200000-000000003fffffff: RAM
 6. 0000000040000000-00000000401fffff: RESERVED
 7. 0000000040200000-00000000acecffff: RAM
 8. 00000000aced0000-00000000acffffff: CONFIGURATION TABLES
 9. 00000000ad000000-00000000af9fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 0000000100000000-000000024f5fffff: RAM
Wrote coreboot table at: acfed400, 0x27c bytes, checksum 87d2
coreboot table: 660 bytes.
FREE SPACE  0. acff5400 0000ac00
CAR GLOBALS 1. aced0200 00000200
USBDEBUG    2. aced0400 aced0600 00010000
MRC DATA    4. acee0600 00000c00
ROMSTAGE    5. acee1200 00000200
GDT         6. acee1400 00000200
ACPI        7. acee1600 0000b400
GNVS PTR    8. aceeca00   00000800
ACPI RESUME10. aceed400 00100000
COREBOOT   acfed400CBFS: located payload @ fff328f8, 273770 bytes.Loading segment from rom address 0xfff328f8
  code (compression=1)
  New segment dstaddr 0x8200 memsize 0x1aba4 srcaddr 0xfff3294c filesize 0x93e8
  (cleaned up) New segment addr 0x8200 size 0x1aba4 offset 0xfff3294c filesize 0x93e8
Loading segment from rom address 0xfff32914
  code (compresstaddr 0xed up) New segment addr 0x100000 size 0xb95d4 offset 0xfff3bd34 filesize 0x3992e
Loading segment from rom address 0xfff32930
  Entry Point 0x00008200
Bounce Buffer at acdae000, 1185292 bytes
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001aba4 filesz: 0x00000000000093e8
lb: [0x0000000000100000, 0x0000000000168038)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001aba4 filesz: 0x00000000000093e8
using LZMA
Clearing0x00000075 memsz000000007a2f
dest 00008200, end 00022da4, bouncebuffer acdae000
Loading Segment: addr: 0x00000005d4 filesz: 0x0000000000lb: [0x0000000000100000, 0x0000000000168038)
segment: [0x0000000000100000, 0x000000000013992e, 0x00000000001b95d4)
 bounce: [0x00000000acdae000, 0x00000000acde792e, 0x00000000ace675d4)
Post relocation: addr: 0x00000000acdae000 memsz:000000b95d4 filesz: 0x00using LZMA
[ 0xacdae000, ac0xace675d4) <- fff3bd34dest acd5d4, bouncebuffer acdae000
move suffix around: from ace16038, to 168038, amount: 5159c
Loaded segments
PCH watchdog disabled
code at 00008200
CPU0: stack: 00163000 - 00164000, lowest used address 00163a80, stack used: 1408 bytes
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x000buffer   = 0xacd
1
mark gross's profile photoJohn Lewis's profile photo
7 comments
 
Not as far as I'm aware. But, it was 6 months ago so I could be wrong.
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mark gross

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I saw this in Escape from NY pizza - PDX .  I thought it was a funny generalization of the US citizen world view.
5
Steven Rostedt's profile photoAlison Chaiken's profile photo
2 comments
 
Too close to the truth to be funny.
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I'm a nerd-god (I took a test on the internet and it said so...first try.  It must be true.) 

I do a lot of Android a linux stuff at work as well as DIY/Maker and assorted hackery on my free time.
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I had the Burro Acapulco (sp?) (sea food burrito) with outdoor seating after a my first 10+ mile bike ride of the year. It was all awesome. Until I accidentally left my kindle on the table but, they held it for me to pick it up 2 hrs later saving the day for me! So now I'm writing this review. Great food, great people, and for today anyway great weather.
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I really trust the work and car advice I get from Steve and Tim. The work is always well done and I really enjoy doing business with them. Also the prices for parts and labor are honest and very competitive. I've never felt ripped off in the years I've been taking our cars to these guys.
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Nice place to relax. Good tunes and a view of a canal.
Food: Very GoodDecor: Very GoodService: Very Good
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