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SemiWiki
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The Semiconductor Wiki Project
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Mentor gets Busy at DVCon - You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there's a panel and of course they’ll be on the exhibit floor. I’ll start with an

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CEO Interview: Srinath Anantharaman of ClioSoft - It will soon be 20 years since ClioSoft started its journey of selling design management software for the semiconductor industry. It was a slow start considering that designs were

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Mentor Plays for Keeps in Emulation - EDA has always been a fiercely competitive market, no more so than in emulation where the clash of claims and counter-claims can leave those of us on the sidelines wondering who’s really on top. Sales are the obvious indicator but leadership there flips back and forth between product releases. That makes Mentor’s choice to play a long game all the more interesting. This week they announced their Veloce Strato platform, raising the bar on specs again but...

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Could China Take the Lead in Installed 300mm Capacity? - China buys more than half of the semiconductors manufactured in the world and yet only produces less the 10% of their own demand. Recently there have been a lot of announcements out of China about large scale investments in semiconductor manufacturing. The Chinese government for example has announced plans to invest $161 billion dollars over ten years in semiconductor manufacturing. In terms of specific announcements Tsinghua Unigroup...

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Four Barriers to Using an SoC for IoT Projects - I often read about the large number of expected IoT design starts around the world, so I started to think about what the barriers are for launching this industry in order to meet the projections. One of my favorite IoT devices is the Garmin Edge 820, a computer for cyclists that has sensors for speed, cadence, power, heart rate, altitude and temperature. The Edge 820 also communicates with Bluetooth and ANT+ wireless protocols, and has GPS to...

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Aldec Rounds Out ALINT-PRO Checker - If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor automatically sets the RTL up correctly” and variants on these confident statements of infallibility.

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Using HSPICE StatEye to Tackle DDR4 Rail Jitter - The world is a risky place, according to Scott Wedge, Principal R&D Engineer at Synopsys, who presented at the Synopsys HSPICE SIG on Feb 2nd in Santa Clara. Indeed, the world circuit designers face can be uncertain. Dealing with risk and departure from ideal was a main theme in the fascinating talks at this dinner event, which is held every year in conjunction with DesignCon. Scott focused on how it is possible to overcome uncertainty throu...

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Xilinx vs Altera Update 2017 - I truly miss the Xilinx versus Altera war of words (competition at its finest) and competition is what makes the fabless semiconductor ecosystem truly great, absolutely. So with great disappointment I read the Intel Analyst Day transcript published by Bloomberg last week. It is attached at the bottom in case you are interested but to me it is a 41 page snoozefest. Here is the detailed (sarcasm) update on the Programmable Solutions Group (Altera) from Intel CEO...

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The Next Big Thing in Deep Learning - I mentioned adversarial learning in an earlier blog, used to harden recognition systems against bad actors who could

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Making Functional Simulation Faster with a Parallel Approach
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