Microsemi updates the Igloo series of FPGAs with Igloo2.
The two biggest changes I notices was:
* New node, goes from 130 nm with Igloo to 65 nm with Igloo2.
* The old "VersaTile" is not replaced by a more "industry standard like" 4LUT based logic block solution.
* Some new hard IP for memory, communication and the likes
* New bigger logic elements range 6,060-146,124 (LUT4 + DFF)
For people not familiar with the Igloo/ProASIC3 families the biggest differentiator is the fact that they are build on a Flash process, compared the common SRAM. The Igloo family was also very small in packages sizes, same architecture as ProASIC3 but smaller packages. Some pros of the flash process is that no external memory is needed for the bitstream, you get a fast startup and low power consumption. They also have a "flash freeze" function that works more or less like the sleep function on your PC, if used correctly a MCU can "freeze" the FPGA at times it's not needed to save power without completely shutting it off. In theory a great feature, not sure how much it can be used in practice. Possible drawbacks, I think, would be that the flash process should in theory be slower. I don't think you can run them as fast as SRAM based FPGAs but would be fun to hear if someone have compared them, just reading some datasheets might give a good hint. The biggest device is still not as big as some from competitors. The Libero tools might not be as good as Xilinx and Alteras, just my opinion, but best is to try it out yourself.. Price wise I'm not sure how the prices weigh up, always hard to compare in general...
Interesting devices either way, I like what I see, a subsidized devkit for $99 will become available in September (standard price $300), looks like a nice devkit.
12 minute video introducing the new line, a little bad sound but otherwise good video:http://soc.microsemi.com/videos/IGLOO2_FPGAs.html #FPGA #Microsemi #Igloo2