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R. Colin Johnson
Works at EETimes - United Business Media
Attended Washington University (M.A.)
Lives in Portland, Oregon
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Moore's Law was a moving target from the beginning starting with doubling transistors every year, to every 18 months, to every 2 years and now we are quickly approaching a brick wall at 5 nanometer. But I have faith in the engineering community to overcome any obstacles in the way, even if we can't see the solutions today.
Moore's law is still alive and kicking after 50 years, but here are the technologies that are busting and boosting it in the 21st century.
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Standardized testing for 3-D chips by Semiconductor Research Corp. and Duke University for IBM, Intel, Freescale, TI, AMD, GlobalFoundries Analog Devices, Qualcomm, Mubadala Technologies.
The Semiconductor Research Corp. has standardized Design-for-Test method for 3D chips that has fast throughput by using a single probe to touch several TSV microbumps at the same time.
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Lowest power MEMS sensor hub yet--using on 75 microWatts at full speed--could enable a whole new era of wearables by extending their battery life to days or even weeks.
QuickLogic announced the world's lowest power sensor hub greatly extending the lifetime of wearables.
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The National Nanotechnology Initiative wants your vote on which of its college student projects sounds the most interesting to you. Go online and vote today.
The National Nanotechnology Initiative opens going voting on its best and brightest projects by clicking on its image in a special gallery.
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The future of integrated circuits is alway revealed each year at the Association for Computing Machinery's (ACM's) International Symposium for Physical Design (ISPD), which also sponsors a contest to solve today's most vexing design problems. 
The contest winners for the Association for Computing Machinery's ACM's) International Symposium on Physical Design (ISPD) are enumerated as well as Kurt Antreich who was honored for his outstanding achievements.
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Qualcomm is getting close to first-silicon on its 3-D VLSI project which will stack layers of CMOS using tiny traditional via to reduce die area by 50%, according to Karim Arabi, vice president of engineering at Qualcomm at the International Symposium of Physical Design (ISPD-2015).
Qualcomm is doing extensive research into how to build 3D structures on a single die without having to use through-silicon-vias (TSVs) and hopes to test 3D SoCs soon.
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IBM and Intel duked it out over three super-duper-supercomputer contracts with our U.S. national labs, and IBM won two awards and Intel won one (but is installing a "starter" supercomputer too). China step aside! Read about Oak Ridges plans for its IBM.
The Collaboration of Oak Ridge, Argonne and Lawrence Livermore (CORAL) project financed by the Department of Energy (DoE) will bring home to the U.S. the fastest supercomputers in the world made by Cray, IBM, Intel and Nvidia.
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STORE DATA IN CLOUD FOR 3 CENTS PER GIGABYTE?
Magnetic tape is the only storage technology keeping up with Moore Law, doubling its capacity ever two years. Now Google, NBC, CBS, Universal and other broadcast and movie houses are using digital data magnetic tape to archive and backup their most precious assets.
IBM set yet another world record in recording density on magnetic tape, maintaining its dominance for archiving and backup, even in the cloud.
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Nanotube circuits can not learn their electronic functions by training the just like neural network software. Will the future chips learn to perform their functions rather than require engineers?
Durham University researchers teach nanotube circuits how to perform their functions by evolutionary learning.
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The Bell Labs Nobel Laureate Garden (below) demonstrates how Bell Labs is continuing to open new doors in basic research, just with a 10-year horizon aimed at improving computing and communications by 10X.
Bell Labs celebrates is forward looking research at the unveiling of the Nobel Laureate Garden. The president Marcus Weldon's look into its future.
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CoolCube 3-D chips, which Qualcomm is helping to finance, will enable any number of CMOS layers to be stacked in tiers--using normal via--by using tungsten on lower layers and copper on top, said Olivier Billoint of the University of Grenoble Alpes (France) at the International Symposium of Physical Design (ISPD-2015).
The University of Grenoble Alpes (France) has developed their CoolCube 3D chips using a monolithic method.
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Analog layout tools on-up expert engineer's designs, but are difficult if not impossible to convince experienced analog layout specialists to use, according to Jurgen Scheible from the Robert Bosch EDA Center at the International Symposium of Physical Design (ISPD-2015).
Reutlingen University has created automated techniques for designing analog circuits, the technology for which it transferred to Cadence, and Rob Rutenbar at the University of Illinois in Urbana described how to convince analog designers use the new tools.
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Introduction
Next-generation electronics and technology news stories published non-stop for 20+ years, R. Colin Johnson's unique perspective has prompted coverage of his articles in a diverse range of major media outlets--from the ultra-liberal National Public Radio (NPR) to the ultra-conservative Rush Limbaugh Show.
Education
  • Washington University (M.A.)
    Philosophy / Symbolic Logic
  • University of Michigan (M.S.)
    Computer, Information and Control Engineering
Basic Information
Gender
Male
Work
Occupation
Technology Editor
Employment
  • EETimes - United Business Media
    Technology Editor, present
  • Electronics Magazine - McGraw-Hill
    Microsystems and Software Editor
  • SlashDot.org
    Contributing Editor, present
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Map of the places this user has livedMap of the places this user has livedMap of the places this user has lived
Currently
Portland, Oregon