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A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary frequency search algorithm (B-FSA), where the frequency search time per cycle is fixed. This eliminates unnecessary clocking times during the frequency comparison process, and thus reduces the total PLL lock time. The additional circuitry needed for A-FSA is only a simple counter controller, thus minimizing hardware overhead. To verify the effectiveness of the proposed algorithm, two wideband PLLs are designed and simulated using a 65-nm CMOS technology: one with B-FSA, and the other with A-FSA. The latter achieves a lock time faster than the former by at least a factor of 2, even under worst case conditions.

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Ternary content-addressable memory

(TCAM)-based search engines generally need a priority

encoder (PE) to select the highest priority match entry

for resolving the multiple match problem due to the don’t

care (X) features of TCAM. In contemporary network security,

TCAM-based search engines are widely used in regular

expression matching across multiple packets to protect against

attacks, such as by viruses and spam. However, the use of PE

results in increased energy consumption for pattern updates

and search operations. Instead of using PEs to determine the

match, our solution is a three-phase search operation that

utilizes the length information of the matched patterns to

decide the longest pattern match data. This paper proposes

a promising memory technology called priority-decision in

memory (PDM), which eliminates the need for PEs and removes

restrictions on ordering, implying that patterns can be stored

in an arbitrary order without sorting their lengths. Moreover,

we present a sequential input-state (SIS) scheme to disable

the mass of redundant search operations in state segments

on the basis of an analysis distribution of hex signatures in

a virus database. Experimental results demonstrate that the

PDM-based technology can improve update energy consumption

of nonvolatile TCAM (nvTCAM) search engines by 36%–67%,

because most of the energy in these search engines is used to

reorder. By adopting the SIS-based method to avoid unnecessary

search operations in a TCAM array, the search energy reduction

is around 64% of nvTCAM search engines.

(TCAM)-based search engines generally need a priority

encoder (PE) to select the highest priority match entry

for resolving the multiple match problem due to the don’t

care (X) features of TCAM. In contemporary network security,

TCAM-based search engines are widely used in regular

expression matching across multiple packets to protect against

attacks, such as by viruses and spam. However, the use of PE

results in increased energy consumption for pattern updates

and search operations. Instead of using PEs to determine the

match, our solution is a three-phase search operation that

utilizes the length information of the matched patterns to

decide the longest pattern match data. This paper proposes

a promising memory technology called priority-decision in

memory (PDM), which eliminates the need for PEs and removes

restrictions on ordering, implying that patterns can be stored

in an arbitrary order without sorting their lengths. Moreover,

we present a sequential input-state (SIS) scheme to disable

the mass of redundant search operations in state segments

on the basis of an analysis distribution of hex signatures in

a virus database. Experimental results demonstrate that the

PDM-based technology can improve update energy consumption

of nonvolatile TCAM (nvTCAM) search engines by 36%–67%,

because most of the energy in these search engines is used to

reorder. By adopting the SIS-based method to avoid unnecessary

search operations in a TCAM array, the search energy reduction

is around 64% of nvTCAM search engines.

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the logic size, propagation delay, power of applications, based upon this improvement the adder design logic size will reduced year by year, here a proposed In recent technology of any application, adders is a more priority to do a function and task of arithmetic operation, in crucial this adder based arithmetic operation will decide work of this paper will design using a single bit full adder to design a multiplier. In this multiplier design, adder is a main priority to reduce the arithmetic logic size and increases speed of multiplier, in recent we have lots of multiplier design, Vedic multiplier, Wallace tree multiplier, booth multiplier, approximate multiplier. Here, the proposed work will taken truncated multiplier design, it's because, the truncated multiplier will have a capability to reduced internal and external architecture size in every design, regarding this truncated multiplier will have three options such as rounding, deleting, truncating, here the MSB bits will be truncated and present the output of n x n multiplication will provided only n bit level, using this truncated multiplier the proposed work will designed a 8-Tap FIR(Finite impulse response) filter and shown the efficiency of filter design using this CMOS GDI (Gate Diffusion Input) adder design. This proposed work will design in CMOS Logic gate and which 10-T transistor level of full adders with 90um technology, finally proved the terms of area, delay and power.

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