"Dark Silicon" is that portion of the device that needs to be shut down to avoid overheating. In a recent IEDM 2014 short course by ARM's principal engineer Greg Yeric the dark silicon was projected to be "about one-third of total area in the 20nm technology node (including 16/14nm finFETs), increasing to as much as 80% by the 5nm node," as reported by a recent Darker Silicon blog. Unlike the time that dimensional scaling could follow Dennard’s Law, it is now getting harder to thin the gate dielectric without causing extreme rise in device leakage and "as a result, while feature sizes have continued to shrink, threshold voltage has not". The following chart is from a DAC ‘13 paper titled The EDA Challenges in the Dark Silicon Era:
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