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The Advance Program for ITC2014 is now posted on the ITC website. use this link to view or download a copy. This is kind of a live document so there will be updates over the weeks leading up to ITC in October.

Enjoy:


http://www.itctestweek.org/files/2014_Advance_Program.pdf
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The Plenary Panel Session at the International Test Conference, a new event this year on Wednesday October 22, includes a slate of panelists with over 200 combined years of experience. The panelists will share their perspectives on how test is a significant reason behind the unprecedented success of the semiconductor industry. They will also show how test will play a more prominent role going forward as electronics become even more pervasive with the emergence of wearables, systems of systems in automotives and bio-medical applications, and the internet of everything.
It would be an injustice to these distinguished individuals to cram their extensive biographies and lists of accomplishments into a short email message like this one. You can learn more by clicking on each person's name, or finding them on the ITC website or in the Advance Program. Even better, attend the Plenary Panel Session to directly receive some "Wisdom from the Giants".

Click here for photos and bios of each participant: conta.cc/1AwOazF
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The International Test Conference has an incredible program for this year's meeting in Seattle. We are pleased to announce the most powerful slate of invited talks in the history of our conference, covering a wide range of topics from the changing characteristics of test in the most advanced (FinFET) technology nodes all the way to the role of test for the internet of everything. Stay tuned for details of our conference, which will be released as our Advance Program in the very near future.

Use this link to see some of the invited speakers that are coming to ITC2014. We hope to see you there as well. 
 
http://conta.cc/1yUkDy6 
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VERY POPULAR TUTORIAL at ITC on Monday Nov 5 - Don't miss it, registration discount available through Friday, October 5
Delay Test: Concepts, Theory and Recent Trends
Presenters S. Natarajan , A. Sinha
Description: This is an advanced tutorial covering fundamental concepts, research ideas and industry practices on validating and testing integrated circuits for speed failures. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test.
The tutorial starts with a discussion of defects and design marginalities that induce a circuit to fail at its rated speed while passing at a lower speed. This is followed by fault models and fault sensitization conditions, covering classical models such as transition faults and path delay faults, and models that capture crosstalk, voltage droop, multiple-input switching and charge-sharing. It then discusses test generation, fault simulation and diagnosis algorithms. design-for-test techniques that facilitate application of delay tests, metrics to measure test quality, and techniques to improve test quality and reduce yield loss are then discussed. Finally, applications in post-silicon validation, speed binning and in-field reliability are discussed using industry case studies.
http://ow.ly/eaYFm
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ITC Proceedings Boxed Sets For Sale at ITC2012
The International Test Conference is proud to offer box sets of conference proceedings from the past 5 years, 2007 – 2011 inclusive. Each box set includes 5 CDs.

The price for each box set is $100, quantities are limited and are available exclusively at ITC2012 conference. Starting this year, this material will only be available online, so don’t miss the opportunity to catch up on any years you might have missed.

Purchase of ITC box sets is managed on the registration area of the website. Box sets can be ordered online through the ITC Registration Page. These must be picked up at ITC2012 registration desk. Quantities are very limited, so order now.
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ITC tutorials continue to provide outstanding value for all who attend. Discount rates are only $395 for IEEE members, $495 for non-members through October 5. After October 5, non-discount rates apply.
 
This years tutorial offering are:

Sunday, November 4
#1: Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability.
#2: Practices in Analog, Mixed Signal and RF Testing
#3: Demystifying Board-Level Test and Diagnosis
#4: Power-aware Testing and Test Strategies for Low-Power Devices
#5: Testing Memories in the Nano-Era: Fault Models, Test Algorithms, Industrial Results, BIST and BISR
#6: The Economics of Test and Test and Testability

Monday, November 5
#7: Mixed-signal DFT and BIST
#8: Delay Test: Concepts, Theory and Recent Trends
#9: Statistical Adaptive Test Methods Targeting “Zero Defect” IC Quality and Reliability
#10: Bridge to Moore – IEEE Standards Provide Access to Debug, Validation and Test of Evermore Complex ICs; on ATE, on Board and in System
# 11: Testing TSV-based 2.5-D and 3-D Stacked ICs
#12: Best Methods and Techniques for Understanding and Optimizing Wafer Sort
Test Week Tutorials. Test Week Tutorials. In 2012 we offer 12 tutorials, six on Sunday, November 4 and six on Monday, November 5. In addition we are providing two test clinics on Mondaay. These tutori...
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ITC Proceedings Boxed Sets For Sale at ITC2012
The International Test Conference is proud to offer box sets of conference proceedings from the past 5 years, 2007 – 2011 inclusive. Each box set includes 5 CDs.

The price for each box set is $100, quantities are limited and are available exclusively at ITC2012 conference. Starting this year, this material will only be available online, so don’t miss the opportunity to catch up on any years you might have missed.

Purchase of ITC box sets is managed on the registration area of the website. Box sets can be ordered online through the ITC Registration Page. These must be picked up at ITC2012 registration desk. Quantities are very limited, so order now.
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In their circles
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International Test Conference is pleased to announce that Dr. Patrice Godefroid, a Principal Researcher at Microsoft Research, will deliver a Keynote Address on Thursday, October 23. This address covers the topic of Automated Software Testing. 

Dr. Godefroid received a B.S. degree in Electrical Engineering (Computer Science elective) and a Ph.D. degree in Computer Science from the University of Liege, Belgium, in 1989 and 1994 respectively. From 1994 to 2006, he worked at Bell Laboratories (part of Lucent Technologies), where he was promoted to "distinguished member of technical staff" in 2001. His research interests include program (mostly software) specification, analysis, testing and verification.

During the last decade, research on automating software testing using program analysis has experienced quite a resurgence. A key technical challenge is automatic code-driven test generation: given a program with a set of input parameters, how to automatically generate a set of input values that, upon execution, will exercise as many program statements as possible. Although automating test generation using program analysis is an old idea, practical tools have only started to emerge over the last few years. This recent progress was enabled by advances in dynamic test generation, automated constraint solving, and modern computers' increasing computational power. All these tools combine techniques from static program analysis (symbolic execution), dynamic analysis (testing and runtime instrumentation), model checking (systematic state-space exploration), and automated constraint solving (SMT solvers). However, they target different application domains and include other original techniques. This talk will present an overview of recent advances on automatic test generation, and discuss applications of these techniques in the software industry.

A key benefit of bringing our conference to Seattle is the ability to tap into local technology excellence from Microsoft Research and other companies. We hope you will join us there in October.

http://conta.cc/1tvjJbh
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Registration for the International Test Conference is open. Please visit the ITC website (www.itctestweek.org) for information about the conference, including links to the Registration Page and the ITC housing page. Register early to qualify for discounted rates. We look forward to seeing you this October in Seattle.

 ITC has negotiated favorable rates at three excellent hotels within walking distance of the Washington State Convention Center; the Sheraton Seattle, the Hyatt Olive 8, and the Crowne Plaza Seattle. We request all attendees who require lodging to use our housing service, to help keep the room rates low. Please use the ITC Housing Page to make all of your ITC hotel reservations.

 ITC Hotel discounts begin on Wednesday October 15 and extend all the way to Tuesday October 28. Attendees who wish to stay for additional time to explore this wonderful region may take advantage of ITC rates within this range of dates. #itctestweek  
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ITC registration opens in 30 minutes. Today's registration hours are 7:30 am to 5:00 pm.
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TUTORIAL 7 – VERY POPULAR
Mixed-signal DFT and BIST: Trends, Principles, and Solutions
Presenters S. Sunter
Description: We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing, such as reducing costs that are increasingly dominated by MS functions. Next, we discuss trends in standardized DFT, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with a review of DFT/BIST techniques, including fault simulation. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and briefly RF. Next seven essential principles of practical analog BIST are presented in detail. Lastly, we discuss the most-practical DFT and BIST techniques, ranging from the classic analog bus, to mostly-digital oversampling and undersampling methods that greatly improve range, resolution, and reusability. Examples and case studies are included. Attendees will gain a clear picture of where they are keeping up with industry, the roadblocks to analog BIST adoption, and how to make parametric DFT/BIST, diagnosis, and testing more systematic. http://ow.ly/e6vGG
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Visit Evaluation Engineering on the exhibits floor at ITC. See http://bit.ly/na5GBA to find out who else is exhibiting. #itctestweek
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Story
Tagline
Premier conference for Test Engineering professionals from Industry and Academia.
Introduction
WELCOME TO ITC's BRAND PAGE

International Test Conference is the world's premier venue dedicated to the electronic test of devices, boards and systems. ITC covers the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, failure analysis and back to process and design improvement. At ITC, design, test, and yield professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

ITC, the cornerstone of the Test Week™ event, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, a lecture series, commercial exhibits and presentations, and a host of ancillary professional meetings.

Please join us in November when we return to the Disneyland Hotel in Anaheim California.