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Calypto Design Systems
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Read Anand Iyer's, director of product marketing for the low power platform, comments on Semiconductor Engineering regarding the key #challenge in #mobility today. 
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Watch our President & CEO's interview with EDA Café at #DVCon. http://goo.gl/ZpdZFs #SemiEDA  #HLS #Power
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Read about our #record #revenue, great start to #2014 and what this year holds for us! http://goo.gl/pW3bk9
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Calypto Design Systems

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EE Journal New Article! "Aye Calypto: Could the Little #ESL Company be the Next Synopsys?" 
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We are excited to see you next week at DVCon! We will be showcasing solutions ranging from Low-Power RTL Design to C Based Design & Verification at booth 804. Media Alert: http://goo.gl/fLWZOH
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Find out why #switching #activity is a critical element of #power #analysis and power #optimization in Rob Eccle's post: "Switching Activity And The Unknown" in Semiconductor Engineering.
http://semiengineering.com/switching-activity-and-the-unknown/
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Thomas Bollaert's excerpts from SemiEngineering's roundtable at DVCon: "High Level Synthesis Grows Up". #SemiEDA #HLS 
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"The results that #HLS can produce have improved enormously in the last year or two, so if you looked at the technology a few years ago and decided it wasn't quite ready yet then take another look." from SemiWiki's latest blog "Calypto: the View From the Top"
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Last day @dvcon ! Stop by our booth for your Calypto M&M fix to #optimize your #power through the afternoon! #semiEDA 
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We are hiring! #FAE, #PMM and more! Email us your résumé jobs@calypto.com.#SemiEDA #jobs #jobsearch #jobs2014
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People
Have them in circles
88 people
Sumit Roy's profile photo
Aanchal Joshi's profile photo
Ahmed Bougandoura's profile photo
Defendor Chen's profile photo
Mathilde Karsenti's profile photo
Grace Liu's profile photo
Michael Pruiksma's profile photo
Todd Burkholder's profile photo
Patrick Hopper's profile photo
Contact Information
Contact info
Phone
(408) 850-2300
Email
Fax
(408) 850-2321
Address
1731 Technology Drive, Suite 340 San Jose, CA 95110
Story
Tagline
Design - Optimize - Verify
Introduction

Calypto's best-in-class technologies focus on high-level synthesis, RTL power optimization and functional verification.

Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows.

PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs.

SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models.

The company, with headquarters in San Jose, California, has offices in Japan, India, Europe, and North America. Calypto's customers include Fortune 500 companies worldwide, including nVIDIA, Qualcomm, Renesas, Freescale Semiconductor and STMicroelectronics. The company has partnerships with several Electronic Design Automation (EDA) companies, including Synopsys, Inc., Mentor Graphics, and Cadence Design Systems.