"Google's VP8/9 project:
- Development time using SystemC/C++ is 50% less than RTL. It took 6 months (including training and learning) vs 1 year for RTL flow.
- Area and timing results comparable to RTL design.
- C-coding was much more compact. 69K C lines vs 300K RLT lines.
- C++ simulation run time is ~50X faster than RTL."
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Calypto® Design Systems is a leading provider of tools for high-level synthesis, RTL power analysis and optimization, and sequential logic equivalency checking. High-level synthesis is an essential methodology for IP development where algorithms and implementations must evolve at a rapid pace, as often occurs in applications such as HEVC, image processing, and advanced communication products amongst many others. Calypto’s patented, deep sequential analysis technology finds low-power optimizations in RTL that other solutions miss, resulting in optimal power-efficient RTL.
Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows.
PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs.
SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models.
Calypto has offices in Europe, India, Japan, Korea, and North America with representation in China, Israel, and Taiwan.