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Calypto Design Systems
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Find out how adopting #finFET processes is an effective way to reduce #power. 
Just because you migrate to the finFET process doesn’t mean you get the expected results.
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“There are two issues here,” said Anand Iyer, director of marketing for the low power platform. “One of them is latency. The second is what is the real information being transferred, and how much #data is being wasted. And with that you need to do the computing that is necessary, not wasted computing. That’s how you eliminate wasted #power.” Continue reading on Semiconductor Engineering​. 
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We are looking forward to seeing you next week at DVCon booth #402! We will also be in the Accellera DVCon Luncheon: "What is Needed to Drive Design Efficiency?" on Monday and the Poster Session where Bryan Bowyer will be presenting on “Closing Functional and Structural Coverage on RTL Generated by HLS” on Tuesday at 10:30 AM at the Gateway Foyer.
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Find out about #Design Exploration Using the #PowerPro Tool!
Obtain significant power savings with no impact to the rest of the design flow.
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Catch up on how "#Catapult 8 represents yet another fundamental renewal of an #EDA tool for improving ease of use and quality of results." in EE Journal's recent blog. 
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Tune into Mark Milligan in Amelia's Fish Fry "Plan 8 from Outer Space
Calypto’s #Catapult 8 Takes Us Higher" and hear him reveal the mysteries of Catapult 8! #SemiEDA  
Bob killed the headlights and put the car in park. We sat in silence. Eerie lights danced on the horizon. First east, then west, and then straight up into the night sky. We watched with mouths agape as the lights came closer (and closer), only to quietly fade away. A UFO in our midst? Not quite. HLS. Most of us have been watching the skies in hopes for the arrival of High Level Synthesis for years. Steering today's HLS-powered flying saucer is my...
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Read about our exciting improvements to #Catapult and "unmatched capabilities to make designers more productive through #HLS"!
I am a believer of continuous improvement in anything we do; it’s pleasant to see rapid innovation in technology these days, especially in semiconductor space – technology, design, tools, methodologies… Imagine a 100K gates up to 1M gates design running at a few hundred MHz frequency and at technology node in the range of .18 to .35 microns in late 1990s and early 2000 when designers were struggling to optimize PPA and shorten design cycle time. ...
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In their circles
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We are excited to announce that we are jointly sponsoring this year's I LOVE DAC program! Be sure to stop by our booth, 2732, to pick-up your collectable button to be entered into the drawing to win an Apple Watch! Don't forget to show your ‪#‎Flair‬! Register here: http://goo.gl/ULoer4
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Did you miss Bryan's Poster Session: "Closing Functional and Structural Coverage on RTL Generated by HLS" at DVCon​ this AM? Get the corresponding White Paper here: http://goo.gl/ZnxeL9 #DVCON   #SemiEDA   #HLS   #RTL  
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Shorten your learning curve from RTL to #HLS using C++ or SystemC coding! Learn more about #Catware: our new library of 1D signal processing hardware ready to use in an HLS Flow.
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A comprehensive overview of Catapult 8. "Third-generation toolsets like Catapult 8 expand beyond traditional top-down approaches to embrace more designer-controlled bottoms-up techniques." Continue reading... #SemiEDA 
High-level synthesis (HLS) is a trend that BDTI has been following for quite some time, beginning with its several-decade-old academic foundations.
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John Cooley's #DAC Trip Report is out! 
"Google's VP8/9 project:
    - Development time using SystemC/C++ is 50% less than RTL.  It took 6 months (including training and learning) vs 1 year for RTL flow.
    - Area and timing results comparable to RTL design.
    - C-coding was much more compact.  69K C lines vs 300K RLT lines.
    - C++ simulation run time is ~50X faster than RTL." 
Continue reading....
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People
In their circles
269 people
Have them in circles
107 people
Simon Waters's profile photo
Vishnu Kanwar's profile photo
Nationwide Businesses's profile photo
Hiba Dweib's profile photo
Raul Romero's profile photo
The Precision Alliance (TPA)'s profile photo
Winmate's profile photo
Ong Wolak's profile photo
Blue Streak Electronics's profile photo
Contact Information
Contact info
Phone
(408) 850-2300
Email
Fax
(408) 850-2321
Address
1731 Technology Drive, Suite 340 San Jose, CA 95110
Story
Tagline
Design - Optimize - Verify
Introduction

Calypto® Design Systems is a leading provider of tools for high-level synthesis, RTL power analysis and optimization, and sequential logic equivalency checking. High-level synthesis is an essential methodology for IP development where algorithms and implementations must evolve at a rapid pace, as often occurs in applications such as HEVC, image processing, and advanced communication products amongst many others. Calypto’s patented, deep sequential analysis technology finds low-power optimizations in RTL that other solutions miss, resulting in optimal power-efficient RTL. 

Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows.

PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs.

SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models.

Calypto has offices in Europe, India, Japan, Korea, and North America with representation in China, Israel, and Taiwan.