My 20% project, I suspect, will be finishing up all the other stuff I couldn't accomplish in 80% of the time.
I don't think most engineers actually do a 20% project, unless they have a really good idea and even then it's a 120% project. I have a few ideas about FPGA cellular autonoma string recognition, but they will have to wait. I think I'll just be writing Python scripts at first. If I'm lucky, I'd like to try adding zero-buffer copy networking to the kernel, like we did at TGV.